1. Field of the Invention
The present invention relates to a flat panel display device, and more particularly, to a flat panel display device for a small module application. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for a reliable operation and small module application.
2. Discussion of the Related Art
Cathode ray tubes (CRTs) have been widely used for display devices such as a television and a monitor. However, the CRTs have some disadvantages, for example, heavy weight, large volume and high driving voltage. Accordingly, flat panel display (FPD) devices, such as liquid crystal display (LCD) devices and organic electroluminescent display (ELD) devices, having excellent characteristics of light weight and low power consumption have been the subject of recent researches.
In general, an LCD device is a non-emissive display device that displays images by a refractive index difference utilizing optical anisotropy properties of a liquid crystal material interposed between an array substrate and a color filter substrate. On the other hand, an ELD device is an emissive display device using an electroluminescent (EL) phenomenon that light is emitted from a luminescent layer when an electric field is applied. The ELD device can be classified into inorganic and organic types according to a source generating an excitation of carriers. Especially, an inorganic type ELD device has been widely used because of its capabilities of displaying full color and moving images, high brightness, and low driving voltage.
The FPD devices such as LCD devices and ELD devices have a circuit unit and a display panel. The circuit unit converts RGB (red, green, and blue) data and control signals of the external driving system into pertinent electrical signals and the display panel shows images to users by using the electrical signals.
Recently, an active matrix type display panel in which a plurality of pixels are disposed in matrix and a thin film transistor (TFT) is formed at each pixel as a switching device is widely used.
FIG. 1 is a schematic block diagram illustrating a related art active matrix display panel 10 and a circuit unit 40 connected to the display panel. In FIG. 1, a display panel 10 includes first and second substrates (not shown) facing into each other. A plurality of gate lines 14 parallel to one another and a plurality of data lines 18 parallel to one another are disposed between the first and second substrates. The plurality of gate lines 14 cross the plurality of data lines 18, thereby defining a plurality of pixel regions “P” in matrix.
FIGS. 2A and 2B are schematic diagrams illustrating a pixel region when a display panel is a liquid crystal panel for a liquid crystal display (LCD) device, and when an organic electroluminescent panel for an organic electroluminescent display (ELD) device, respectively.
As shown in FIG. 2A, each pixel region “P” includes a switching thin film transistor (TFT) “TS” as a switching device, a liquid crystal capacitor “CLC”, and a storage capacitor “CST”. The liquid crystal capacitor “CLC” includes a pixel electrode and a common electrode facing into each other, and a liquid crystal layer interposed between the pixel electrode and the common electrode. The TFT “TS” includes a gate electrode connected to the gate line 14, a drain electrode connected to the data line 18, a source electrode connected to the pixel electrode, an active layer which is a path for electrons and holes, and an ohmic contact layer. The storage capacitor “CST” is connected to the liquid crystal capacitor “CLC” in parallel to resolve a parasitic capacitance problem resulting from the pixel design.
As shown in FIG. 2B, each pixel region “P” includes a switching TFT “TS”, a driving TFT “TD”, an emission diode “D”, and a storage capacitor “CST”. The emission diode “D” includes an anode and a cathode facing into each other, and an organic emission layer interposed between the anode and the cathode. The switching TFT “TS” includes a gate electrode connected to a gate line 14, a drain electrode connected to a data line 18, a source electrode connected to a gate electrode of the driving TFT “TD”, an active layer and an ohmic contact layer. The storage capacitor “CST” is connected to the gate electrode and a drain electrode of the driving TFT “TD”.
Referring back to FIG. 1, the circuit unit processes RGB (red, green, and blue) data and control signals transmitted from the external driving system and supplies the display panel 10 with the processed RGB data and the control signals. The circuit unit 40 includes a timing controller 32, a level shifter 34, a power supply 36, a gate driver 12, and a data driver 16. When the active layer of the switching TFT “TS” and the driving TFT “TD” is formed of polycrystalline silicon, a portion of the circuit unit 40 can be formed in the display panel 10. The gate driver 12 is disposed at a first edge of the display panel 10 and connected to the gate lines 14. The data driver 16 is disposed at a second edge of the display panel 10 adjacent to the first edge and connected to the data lines 18.
The timing controller 32 processes the RGB data and the control signals transmitted from the external driving system and outputs gate and data control signals. The control signals include a vertical sync signal “Vsync” of a frame discrimination signal, a horizontal sync signal “Hsync” of a line discrimination signal, a data enable signal “DE” indicating a time for data input and a main clock “MCLK” as timing sync signals. The timing controller 32 rearranges the RGB data and outputs the data control signals for driving the display panel 10 according to the timing sync signals to the data driver 16. The data control signals include RGB digital data (R(0, N), G(0, N), B(0, N)), a horizontal sync signal “Hsync,” a horizontal line start signal “HST” which forces to start to input the RGB data to the data driver 16 and a source pulse clock “HCLK” for a data shift in the data driver 16. Moreover, the timing controller 32 outputs the gate control signals to the gate driver 12. The gate control signals include a vertical sync signal “Vsync”, a vertical line start signal “VST” which forces to start to input a gate-on-signal to the gate driver 12, and a gate clock “VCLK” for sequentially inputting the gate-on-signal to the respective gate lines 14.
The power supply 36 includes a gate driving voltage generator 36a, a DC/DC (direct current/direct current) converter 36b and a gray level voltage generator 36c. The gate driving voltage generator 36a outputs a gate-on-voltage “Von” for the gate-on-signal and a gate-off-voltage “Voff” for a gate-off-signal to the gate driver 12. The DC/DC convert 36b outputs a DC voltage for driving each element of the display panel 10 and the circuit unit 40. The gray level voltage generator 36c generates and outputs a gray level voltage to the data driver 16 according to the bit number of the RGB data and a gray level reference voltage transmitted from the external circuit.
The data driver 16 including a data shift register (not shown) generates a latch clock by shifting the horizontal sync signal “Hsync” and the horizontal line start signal “HST” with the source pulse clock “HCLK” and selects a pertinent gray level voltage by sampling the RGB digital data for each data line 16 according to the latch clock. The gate driver 12 including a gate shift register (not shown) sequentially enables the gate lines 14 by shifting the vertical sync signal “Vsync” and the vertical line start signal “VST” with the gate clock “VCLK” and outputs the gate-on-voltage “Von” and the gate-off-voltage “Voff” transmitted from the gate driving voltage generator 36a. Thus, each switching TFT “TS” applies the gray level voltage to the liquid crystal capacitor “CLC” or the emission diode “D” according to a scan signal including the gate-on-voltage “Von” and the gate-off-voltage “Voff”.
Although not shown in FIG. 1, the data shift register and the gate shift register include a plurality of shift register TFTs formed of polycrystalline silicon. The source pulse clock “HCLK” and the gate clock “VCLK” applied to the shift register TFTs are required to have a voltage-swing greater than about 10 V. Since the shift register TFTs are formed in the display panel 10 by using polycrystalline silicon, the shift register TFTs can reliably function with a clock having a voltage-swing greater than about 10 V. However, since a clock outputted from the timing controller 32 has a voltage-swing of about 3.3 V, the circuit unit 10 includes the level shifter 34 that amplifies the clock to have a voltage-swing greater than about 10 V.
Generally, the level shifter 34 amplify a voltage-swing of about 3.3 V to a voltage-swing greater than about 10 V is composed of integrated circuit (IC) formed on a wafer (i.e., single crystalline silicon). Since a required carrier mobility cannot be obtained when the level shifter 34 is formed in the display panel 10 by using polycrystalline silicon. Moreover, even when the level shifter 34 is composed of IC, it is difficult to combine the level shifter 34 having a voltage level greater than about 10 V and the other elements into a single chip. Accordingly, an additional chip is required for the level shifter 34 and the additional chip including the level shifter 34 is formed on a printed circuit board (PCB) 40. The PCB 40 is connected to the display panel 10 through a flexible printed circuit board (F-PCB) 50.
The timing controller 32 can be formed in the display panel 10. When the timing controller 32 is formed in the display panel 10, however, a driving reliability is reduced and a circuit design becomes complex because all the clocks are outputted from the display panel 10, amplified at the level shifter 34, and inputted back to the display panel 10.
On the other hand, a multiplexer (MUX) can be formed in the display panel 10 instead of the data driver 16, as shown in FIG. 3.
FIG. 3 is a schematic block diagram illustrating another related art active matrix display panel including a multiplexer MUX and a circuit unit connected to the display panel. In FIG. 3, the same elements those of FIG. 1 are represented with the same reference numerals, and descriptions will be omitted for simplicity.
A MUX combines a plurality of data streams into one signal or vice versa. In FIG. 3, a MUX 60 has an input and output ratio of 1:3. The MUX 60 is formed in a display panel 10 instead of a data driver 16 and has a plurality of data lines 18 as output terminals. The data driver 16 at the exterior of the display panel 10 is connected to the MUX 60 through a plurality of input terminals 62. Signals outputted from a timing controller 32 include a MUX clock for driving the MUX 60. The timing controller 32, a level shifter 34, and a power supply 36 are formed on an additional printed circuit board (PCB) 40. The PCB 40 is connected to the display panel 10 through a flexible-printed circuit board (F-PCB) 50 including the data driver 16 composed of an integrated circuit (IC).
The MUX 60 in the display panel 10 includes a plurality of MUX thin film transistors (TFTs). FIG. 4 is a schematic circuit diagram illustrating the MUX of FIG. 3. FIG. 5 is a timing chart illustrating a propagation of a MUX clock of the MUX of FIG. 4 during one frame. In FIGS. 4 and 5, the plurality of MUX TFTs of the MUX 60 are formed of one type of TFT (i.e., a positive metal oxide silicon (PMOS) TFT) for convenience of descriptions.
As shown in FIGS. 4 and 5, when an input and output ratio is 1:3, one of the input terminals 62 (shown in FIG. 3) is connected to each source electrode of three MUX TFTs 64 and each drain electrode of three MUX TFTs 64 is connected to the respective data line 18. Three MUX clocks “Φ1, Φ2, and Φ3” are sequentially inputted into three gate electrodes of three MUX TFTs 64. When one of the input terminals 62 (shown in FIG. 3) outputs a first gray level voltage “Da”, the first gray level voltage “Da” is transmitted into three source electrodes of three MUX TFTs “Ta-1, Ta-2, and Ta-3”. First, second, and third MUX clocks “Φ1, Φ2, and Φ3” are sequentially inputted into three gate electrodes of the three MUX TFTs “Ta-1, Ta-2, and Ta-3”, respectively. Moreover, three drain electrodes of the three MUX TFTs “Ta-1, Ta-2, and Ta-3” are connected to first, second, and third data lines “La-1, La-2, and La-3”. Similarly, these conditions are applied to the other gray level voltages “Db and Dc” of the other input terminals.
Therefore, as shown in FIG. 5, while a scan signal is applied to an n-th gate line “Gn”, the first, second, and third gray level voltages “Da, Db, and Dc” are outputted from the first, fourth, and seventh data lines “La-1, Lb-1, and Lc-1” by the first MUX clock “Φ1”, respectively. Sequentially, the first, second, and third gray level voltages “Da, Db, and Dc” are respectively outputted from the second, fifth, and eighth data lines “La-2, Lb-2, and Lc-2” by the second MUX clock “Φ2”, and respectively outputted from the third, sixth, and ninth data lines “La-3, Lb-3, and Lc-3” by the third MUX clock “Φ3”. These operations are repeated while the scan signal is sequentially scanned from the n-th gate line “Gn” to an m-th gate line “Gm”, thereby displaying an image for one frame.
The number of ICs for the data driver 16 (shown in FIG. 3) and the number of input terminals 62 (shown in FIG. 3) of the data driver 16 can be reduced by forming the MUX 60 within the display panel 10 (shown in FIG. 3). The MUX clocks “Φ1, Φ2, and Φ3” are outputted from the timing controller 32 (shown FIG. 3). Since the timing controller 32 and the data driver 16 are disposed at the exterior of the display panel 10, a plurality of signals transmitted from the timing controller 32 to the data driver 16 do not have to be amplified. Accordingly, data control signals are directly transmitted from the timing controller 32 to the data driver 16 unlike the circuit unit shown in FIG. 1.
However, since the MUX 60 including a plurality of MUX TFTs 62 of polycrystalline silicon is formed on the display panel 10, the MUX clocks transmitted to the plurality of MUX TFTs 62 are required to have a voltage-swing greater than about 10 V, for example, about 18 V. Therefore, original MUX clocks outputted from the timing controller 32 should be amplified to have a voltage-swing greater than about 10 V by the level shifter 34.
It is difficult to form the level shifter 34 on the display panel 10. And, the level shifter is generally composed of an additional IC on the PCB 50 at the exterior of the display panel 10 to have a required carrier mobility. However, this structure makes the circuit unit exterior of the display panel 10 complex and large-sized. Accordingly, it is difficult to apply such a structure to a small-sized module, such as a personal digital assistant (PDA) and a mobile phone. To apply to the small-sized module, the external circuit unit must be small-sized and simplified such that the external circuit unit can be formed in a single semiconductor chip. However, since the level shifter in the related art is formed in the additional chip, the design of the circuit unit exterior of the display panel becomes complex and the display device becomes large.